Scalable NoC Architectures: Efficient and Low Energy Consumption Chip Communication

Energy has been the primary reason for shifting from traditional single-core processors to current multicore processors. Such multicore designs require an interconnection network to communicate cores among themselves and with memory. As the number of cores per chip increases, the energy consumption of these Networks-on-Chip (NoC) has become comparable to that of the cores computation, to the point of being expected to be the performance bottleneck of near future processors. Novel technologies, such as nanophotonics, have recently appeared as a response to the urgent need for efficient and scalable chip communication. In this paper, different alternatives for the reduction of the NoC power demands are analyzed from the interconnect level up to the microarchitectural level. Additionally, a graphene-enabled wireless/optical-wired communication architecture, consisting on both a photonic NoC and a wireless NoC, is proposed. The former for transferring heavy flows of data, the latter for supporting the control plane of the whole network, and carrying light data flows. Keywords— Network-on-Chip; Efficient Chip Communication; Nanophotonics; Silicon-on-Insulator; Graphene; Plasmonics;